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ADT7473
Example 1
For a PWM duty cycle of 50%
Value (decimal) = 50/0.39 = 128 (decimal)
Value = 128 (decimal) or 0x80 (hex)
Example 2
For a PWM duty cycle of 33%
Value (decimal) = 33/0.39 = 85 (decimal)
Value = 85 (decimal) or 0x54 (hex)
Table 42. PWM CURRENT DUTY CYCLE REGISTERS
Sleep States
The ADT7473/ADT7473 ? 1 has been specifically
designed to operate from a 3.3 V STBY supply. In
computers that support S3 and S5 states, the core voltage of
the processor is lowered in these states. If using the dynamic
T MIN mode, lowering the core voltage of the processor
changes the CPU temperature and the dynamics of the
system under dynamic T MIN control. Likewise, when
monitoring THERM, the THERM timer should be disabled
during these states.
Register
0x30
0x31
Description
PWM1 Duty Cycle
PWM2 Duty Cycle
Default
0xFF (0%)
0xFF (0%)
Dynamic T MIN Control Register 1 (0X36)
Bit <1> V CCP LO = 1
When the V CCP voltage drops below the V CCP low limit,
the following occurs:
0x32 PWM3 Duty Cycle 0xFF (0%)
By reading the PWMx current duty cycle registers, the
user can keep track of the current duty cycle on each PWM
output, even when the fans are running in automatic fan
speed control mode or acoustic enhancement mode. See the
Programming the Automatic Fan Speed Control Loop
section for details.
Fan Presence Detect
This feature can be used to determine if a 4-wire fan is
directly connected to a PWM output. This feature does not
work for 3-wire fans. To detect whether a 4-wire fan is
connected directly to a PWM output, the following steps
must be performed in this order:
1. Drive the appropriate PWM outputs to 100% duty
cycle.
2. Set Bit 0 of Configuration Register 2 (0x73).
3. Wait 5 ms.
4. Program the fans to run at a different speed if
necessary.
5. Read the state of Bits <3:1> of Configuration
Register 2 (0x73). The state of these bits reflects
whether a 4-wire fan is directly connected to the
PWM output.
As the detection time only takes 5 ms, programming the
PWM outputs to 100% and then back to their normal speed
is not noticeable in most cases.
Description of How Fan Presence Detect Works
Typical 4-wire fans have an internal pull up to 4.75 V
? 10%, which typically sources 5 mA. While the detection
cycle is on, an internal current sink is turned on, sinking
current from the fan’s internal pullup. By driving some of the
current from the fan’s internal pullup (~100 m A), the logic
buffer switches to a defined logic state. If this state is high,
a fan is present; if it is low, no fan is present.
1. Status Bit 1 (V CCP ) in Status Register 1 is set.
2. SMBALERT is generated, if enabled.
3. THERM monitoring is disabled. The THERM
timer should hold its value prior to the S3 or S5
state.
4. Dynamic T MIN control is disabled. This prevents
T MIN from being adjusted due to an S3 or S5 state.
5. The ADT7473/ADT7473 ? 1 is prevented from
entering the shutdown state.
Once the core voltage, V CCP , goes above the V CCP low
limit, everything is re-enabled, and the system resumes
normal operation.
XNOR Tree Test Mode
The ADT7473/ADT7473 ? 1 includes an XNOR tree test
mode. This mode is useful for in-circuit test equipment at
board-level testing. By applying stimulus to the pins
included in the XNOR tree, it is possible to detect opens or
shorts on the system board.
Figure 45 shows the signals that are exercised in the
XNOR tree test mode. The XNOR tree test is invoked by
setting Bit 0 (XEN) of the XNOR tree test enable register
(0x6F).
TACH1
TACH2
TACH3
TACH4
PWM2
PWM3 PWM1/XTO
Figure 45. XNOR Tree Test
The PWM input voltage should be clamped to 3.3 V. This
ensures the PWM output is not pulled to a voltage higher
than the maximum allowable voltage on that pin (3.6 V).
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